Pailu D Wang

5789314, Aug 4, 1998

Dec 5, 1995

8/567648

Tong Zhang - San Jose CA
Pailu Wang - San Jose CA
Chuen-Der Lien - Los Altos CA

Integrated Device Technology, Inc. - Santa Clara CA

H01L 214763

438622

A method is provided for suppressing or eliminating void formation during the manufacture of integrated circuits. TEOS is deposited and etched to form recesses that assist in eliminating or suppressing void formation. The recesses may be located in an interlevel layer, or within the oxide layer just beneath the passivation layer.

5831899, Nov 3, 1998

Apr 7, 1997

8/841985

Pailu Wang - San Jose CA
Chuen-Der Lien - Los Altos Hills CA
Kyle W. Terrill - Campbell CA

Integrated Device Technology, Inc. - Santa Clara CA

G11C 1100

365156

A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so that bonding pads in the metal layer are eliminated. In one embodiment, the metal layer includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer.

6100128, Aug 8, 2000

Aug 4, 1998

9/129254

Pailu Wang - San Jose CA
Chuen-Der Lien - Los Altos Hills CA
Kyle W. Terrill - Campbell CA

Integrated Device Technology, Inc. - Santa Clara CA

H01L 218238

438238

A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated. In one embodiment, the metal layer that includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer.

5710449, Jan 20, 1998

May 22, 1996

8/651231

Chuen-Der Lien - Los Altos Hills CA
Pailu D. Wang - San Jose CA

Integrated Device Technology, Inc. - Santa Clara CA

H01L 2976
H01L 2711

257336

Lightly doped active regions in a semiconductor structure reduce occurrences of pipeline defects. The light doped active region are typically employed where performance is not adversely affected. For example, in memory cells, pass transistors have lightly doped drains which directly connect to bit lines. A pass transistor of this type can have the source more heavily doped than the drain. Alternatively, drains and sources of pass transistors are lightly doped. Drains of pull-down transistors can also be lightly doped. The difference in doping of active regions does not increase fabrication processing steps because conventionally active regions are formed by two doping steps to create a lightly doped portions adjacent gates where field strength is highest. The invention changes such processes by covering the desired lightly active regions with the mask used during a second doping process.

6065973, May 23, 2000

Feb 20, 1997

8/802512

Chuen-Der Lien - Los Altos Hills CA
Pailu D. Wang - San Jose CA

Integrated Decice Technology, Inc. - Santa Clara CA

H01L 218244

437 52

Lightly doped active regions in a semiconductor structure reduce occurrences of pipeline defects. The light doped active region are typically employed where performance is not adversely affected. For example, in memory cells, pass transistors have lightly doped drains which directly connect to bit lines. A pass transistor of this type can have the source more heavily doped than the drain. Alternatively, drains and sources of pass transistors are lightly doped. Drains of pull-down transistors can also be lightly doped. The difference in doping of active regions does not increase fabrication processing steps because conventionally active regions are formed by two doping steps to create a lightly doped portions adjacent gates where field strength is highest. The invention changes such processes by covering the desired lightly active regions with the mask used during a second doping process.