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Pailu D Wang

from San Jose, CA
Age ~62

Pailu Wang Phones & Addresses

  • 1087 Kelly Dr, San Jose, CA 95129 (408) 252-2036
  • Boise, ID
  • Santa Clara, CA

Publications

Us Patents

Method Of Topside And Inter-Metal Oxide Coating

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US Patent:
5789314, Aug 4, 1998
Filed:
Dec 5, 1995
Appl. No.:
8/567648
Inventors:
Tong Zhang - San Jose CA
Pailu Wang - San Jose CA
Chuen-Der Lien - Los Altos CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
H01L 214763
US Classification:
438622
Abstract:
A method is provided for suppressing or eliminating void formation during the manufacture of integrated circuits. TEOS is deposited and etched to form recesses that assist in eliminating or suppressing void formation. The recesses may be located in an interlevel layer, or within the oxide layer just beneath the passivation layer.

Local Interconnect Structure And Process For Six-Transistor Sram Cell

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US Patent:
5831899, Nov 3, 1998
Filed:
Apr 7, 1997
Appl. No.:
8/841985
Inventors:
Pailu Wang - San Jose CA
Chuen-Der Lien - Los Altos Hills CA
Kyle W. Terrill - Campbell CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G11C 1100
US Classification:
365156
Abstract:
A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so that bonding pads in the metal layer are eliminated. In one embodiment, the metal layer includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer.

Process For Making Six-Transistor Sram Cell Local Interconnect Structure

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US Patent:
6100128, Aug 8, 2000
Filed:
Aug 4, 1998
Appl. No.:
9/129254
Inventors:
Pailu Wang - San Jose CA
Chuen-Der Lien - Los Altos Hills CA
Kyle W. Terrill - Campbell CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
H01L 218238
US Classification:
438238
Abstract:
A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated. In one embodiment, the metal layer that includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer.

Memory Cell Having Active Regions Without N+ Implants

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US Patent:
5710449, Jan 20, 1998
Filed:
May 22, 1996
Appl. No.:
8/651231
Inventors:
Chuen-Der Lien - Los Altos Hills CA
Pailu D. Wang - San Jose CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
H01L 2976
H01L 2711
US Classification:
257336
Abstract:
Lightly doped active regions in a semiconductor structure reduce occurrences of pipeline defects. The light doped active region are typically employed where performance is not adversely affected. For example, in memory cells, pass transistors have lightly doped drains which directly connect to bit lines. A pass transistor of this type can have the source more heavily doped than the drain. Alternatively, drains and sources of pass transistors are lightly doped. Drains of pull-down transistors can also be lightly doped. The difference in doping of active regions does not increase fabrication processing steps because conventionally active regions are formed by two doping steps to create a lightly doped portions adjacent gates where field strength is highest. The invention changes such processes by covering the desired lightly active regions with the mask used during a second doping process.

Memory Cell Having Active Regions Without N+ Implants

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US Patent:
6065973, May 23, 2000
Filed:
Feb 20, 1997
Appl. No.:
8/802512
Inventors:
Chuen-Der Lien - Los Altos Hills CA
Pailu D. Wang - San Jose CA
Assignee:
Integrated Decice Technology, Inc. - Santa Clara CA
International Classification:
H01L 218244
US Classification:
437 52
Abstract:
Lightly doped active regions in a semiconductor structure reduce occurrences of pipeline defects. The light doped active region are typically employed where performance is not adversely affected. For example, in memory cells, pass transistors have lightly doped drains which directly connect to bit lines. A pass transistor of this type can have the source more heavily doped than the drain. Alternatively, drains and sources of pass transistors are lightly doped. Drains of pull-down transistors can also be lightly doped. The difference in doping of active regions does not increase fabrication processing steps because conventionally active regions are formed by two doping steps to create a lightly doped portions adjacent gates where field strength is highest. The invention changes such processes by covering the desired lightly active regions with the mask used during a second doping process.
Pailu D Wang from San Jose, CA, age ~62 Get Report